Non-zero error method for improving output voltage regulation of low-resolution digital controllers for SMPS

A simple method for achieving tight output voltage regulation in digitally controlled low-power dc-dc switch-mode power supplies with low-resolution digital pulse-width modulators (DPWM) is introduced. By utilizing a non-zero scheme for coding the output voltage error, an inherent quasi sigma-delta modulation effect improving effective DPWM resolution is obtained. The effectiveness of the method is experimentally verified on a 400 kHz, 5 V to 1.8 V, 5 W digitally-controlled buck converter. Using a 6-bit DPWM and the new coding scheme only, undesirable low-frequency limit-cycle oscillations (LCO), existing in conventional designs, are eliminated and tight output voltage regulation obtained.