Functional Verification of a USB Host Controller

With everyday growing demands, complexity of electronic devices has been constantly increasing. Functional verification has become one of the major bottlenecks in the design and verification flow. In order to respond to modern demands, new devices are made of standard pre-verified reusable IP blocks created by using abstract TLM. The paper proposes a three-step design and verification flow based on a reusable test bench. It enables a short design time for a fast-simulating functionally-verified TL model, to be used in early SW development, and a functionally-verified RTL model, ready for HW implementation. The approach is demonstrated on a USB host controller design.