Speed-independent bit-serial multiplier

We propose a novel architecture of an asynchronous bit-serial multiplier based on a mixed-mode delay model. Firstly, the control circuit of the multiplier´s basic cell is designed as a speed-independent circuit. Then we incorporate a data-path function under the bounded-delay model. The crucial idea of the proposed design is that data transfer between basic cells is acknowledged by another data transfer in the opposite direction. Thus, this design solution has resulted in lower hardware complexity and is suitable for architectures with counterflow data streams.