• DocumentCode
    3631833
  • Title

    On the structured parallelism of decoders for LDPC convolutional codes - an algebraic description

  • Author

    Marcos B.S. Tavares;Emil Matus;Gerhard P. Fettweis

  • Author_Institution
    Vodafone Chair, Technische Universit?t Dresden, D-01062, Germany
  • fYear
    2009
  • fDate
    5/1/2009 12:00:00 AM
  • Firstpage
    2453
  • Lastpage
    2456
  • Abstract
    We propose an algebraic framework that captures the parallelism of decoders for LDPC convolutional codes. From this framework, an architectural template of a decoding core is derived and its main aspects are discussed. Furthermore, sophisticated decoding structures are built using the decoding core as basic element.
  • Keywords
    "Decoding","Parity check codes","Convolutional codes","Bipartite graph","Routing","Belief propagation","Memory architecture","Delay","Throughput","Interleaved codes"
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
  • ISSN
    0271-4302
  • Print_ISBN
    978-1-4244-3827-3
  • Electronic_ISBN
    2158-1525
  • Type

    conf

  • DOI
    10.1109/ISCAS.2009.5118297
  • Filename
    5118297
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3631833