• DocumentCode
    3632778
  • Title

    A 47 Gb/s LDPC decoder with improved low error rate performance

  • Author

    Zhengya Zhang;Venkat Anantharam;Martin J. Wainwright;Borivoje Nikolic

  • Author_Institution
    Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USA
  • fYear
    2009
  • Firstpage
    286
  • Lastpage
    287
  • Abstract
    A parallel low-density parity-check (LDPC) decoder is designed for the (2048,1723) Reed-Solomon-based LDPC (RS-LDPC) code suitable for 10GBASE-T Ethernet. A two-step decoding scheme lowers the error floor to a 10−14 BER. The decoder architecture is optimized for area, power, and high throughput. The resulting 5.35 mm2, 65nm CMOS chip achieves a decoding throughput of 47.7 Gb/s. With scaled frequency and voltage, the chip delivers a 6.67 Gb/s throughput while dissipating 144 mW of power.
  • Keywords
    "Parity check codes","Error analysis","Throughput","Maximum likelihood decoding","Frequency","Wiring","Bit error rate","Iterative decoding","Ethernet networks","Voltage"
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2009 Symposium on
  • ISSN
    2158-5601
  • Print_ISBN
    978-1-4244-3307-0
  • Electronic_ISBN
    2158-5636
  • Type

    conf

  • Filename
    5205323
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3632778