• DocumentCode
    3633568
  • Title

    Linearly weighted classifier circuit

  • Author

    Merih Yildiz;Shahram Minaei;Serdar Ozoguz

  • Author_Institution
    Department of Electronics and Communications Engineering, Istanbul Technical University, Maslak, Istanbul, Turkey
  • fYear
    2009
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In this paper a CMOS realization of a linearly weighted classifier circuit which is called classifier block is proposed. The proposed classifier block is composed of Linearly Weighted Circuits (LWC) and CMOS Core Circuits (CC). The proposed circuit can classify linearly non-separable data. The weights of the classifier circuit are achieved with LWC blocks. Using 0.35 μm AMS technology parameters, SPICE simulation results for a LWC and classifier block are included to verify the expected results.
  • Keywords
    "Artificial neural networks","Transconductance","Electronic mail","CMOS technology","SPICE","Circuit simulation","Target recognition","Object recognition","Pattern recognition","Artificial intelligence"
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA ´09. Joint IEEE North-East Workshop on
  • Print_ISBN
    978-1-4244-4573-8
  • Type

    conf

  • DOI
    10.1109/NEWCAS.2009.5290438
  • Filename
    5290438
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3633568