Implementation of a radix 2/sup n/ multiplier using high performance logic

In this study, a 16/spl times/16 bit radix 2/sup n/ multiplier was implemented using high performance logic. The design was done in a bottom-up style, where the performance of each block in the corresponding hierarchy was optimized starting from the transistor level. The performance of the radix 2/sup n/ multiplier was compared with some existing multipliers.