Wrapper tool – learning and application of digital system testability to SoC cores

The presented tool is an interactive training instrument for understanding the wrapper design for digital system testability. It consists of two modules: Learning and Application modules. The application module offers several setup options to configure a generated core test wrapper in VHDL. The setup options also provide unique optimization techniques for scan elements ordering in parallel lines. Another technique generates a reconfigurable parallel lines architecture which provides efficient application of internal and external tests to a test wrapper without significant increase of the area.