3D hybrid integration and functional interconnection of a power transistor and its gate driver

3D packaging and hybrid heterogeneous integration are currently attracting considerable interest in the literature. In most publications, the power dies and their respective gate drivers are interconnected using flex or PCB layers. Apart from a few exceptions, packaging is mainly based on separate power and driver dies, focusing on improving the performance of individual chips. This paper presents a different approach in which the design of the power and gate driver chips takes the interconnection of the two dies into account. This method is used in order to simplify and optimize packaging and interconnections and to improve the overall performance. The basic idea is to flip chip the integrated gate driver directly onto the power die, resulting in the 3D heterogeneous assembly of a vertical power device and a CMOS integrated gate driver. In order to simplify the implementation of this solution, the gate driver supply, its storage capacitor and the control signal insulation unit are also integrated and interconnected in and on the two silicon dies.