Parallel Hardware Implementation of Connected Component Tree Computation

The paper proposes a new parallel hardware architecture for a connected component tree computation. It is an original implementation of the recently published parallel algorithm based on building of a 1D tree for each individual image line and their progressive merging. The image is divided into independent partitions which are processed concurrently. Nevertheless, merging of these partitions requires access to all partitions. A special interconnection switch is proposed to solve this problem. The implementation results obtained on an FPGA are also presented. The obtained performance on Virtex 5 FPGA is 145 Mpx/s using 11 928 slice LUTs, 5752 registers and 8064 Kib of block RAM.