Multiprocessor scheduling with a priori node assignment

Compile-time scheduling of DSP programs on multiprocessor systems is discussed. Contrary to standard approaches, a complete, a priori node assignment is supposed. The assumption is justified for coarse-grain DSP programs on heterogeneous programmable architectures with dedicated memory, I/O or accelerator units. The a priori information about cut arcs is used to apply the retiming transformation for the minimization of the schedule length. Experimental results show that the obtained improvement is worth the additional complexity which is introduced by retiming. At the end, issues related to the implementation of retimed DSP programs are discussed.