SPADIC — A self-triggered pulse amplification and digitization ASIC

For the readout of the TRD sub-detector of the planned fixed-target CBM experiment at FAIR/GSI (Darmstadt, Germany), a new self-triggered amplification and digitization mixed-signal chip is being developed. The final asic will have 32–64 channels each composed of a low noise and power charge preamplifier, a 7–9 Bit pipeline ADC running at about 25 MSamples/s and some digital data processing units carrying out detector specific tasks such as ion-tail cancellation and baseline correction. A token ring network will act as a balancing arbiter between the channels and the output serializer. The latest 180 nm test-chip has 26 preamplifier/shaper channels and 8 ADCs. For control signal generation and output decoding two synthesized blocks have also been integrated. By connecting both preamplifier and ADC, digital snap-shots of injected test-pulses have been recorded successfully, showing the proper oscilloscope-like operation of the whole mixed-signal data chain from analog amplification to digital output encoding.