Scaling of SOI FinFETs down to fin width of 4 nm for the 10nm technology node

Using a novel replacement gate SOI FinFET device structure, we have fabricated FinFETs with fin width (D_Fin) of 4 nm, fin pitch (FP) of 40 nm, and gate length (L_G) of 20 nm. With this structure, we have achieved arrays of thousands of fins for D_Fin down to 4 nm with robust yield and structural integrity. We observe performance degradation, increased variability, and V_T shift as D_Fin is reduced. Capacitance measurements agree with quantum confinement behavior which has been predicted to pose a fundamental limit to scaling FinFETs below 10 nm L_G.