An application of a N-P switch for a construction of current-mode gates

From the output of a current-mode gate in the low logical state a residual current of a value greater than zero flows. Connecting the outputs of several gates in node causes aggregation of residual currents and the sum can exceed the limit ½ of a current corresponding with a logical state “1”. This phenomenon makes the construction of the current-mode gates working in a multi-value logic impossible. The change of the concept of building of the current-mode gate by the application of the modified key for the residual current reduction is proposed. The current switching key in a circuits of current-mode gate was developed. It was used for the construction of the new inverter output module. The new realisation of the current- mode, inverter type gate was tested in a simulation. An attempt to build the current-mode gate working in multi-value logic (MVL) was taken. The satisfactory result of simulation of the MVL current-mode gate shows, that the application of MVL gates in digital systems in practical realisations is possible. The MVL application in digital systems allows to decrease the hardware complexity of ASICs.