Analysis and the design of a first - order ΔΣ modulator using very incomplete settling

One of the main building blocks of a Delta-Sigma modulator (ΔΣM) is the integrator circuit. Usually this is implemented either in discrete or in continuous time domains using amplifiers. This paper analyses a ΔΣ circuit based on the implementation of passive switched-capacitor (SC) integrator using very incomplete settling. The behavior of a 1^st order ΔΣM is fully analyzed and explained. Electrical simulations show that the ΔΣM achieves a peak signal-to-noise-plus-distortion ratio (SNDR) of 62 dB, a peak signal-to-noise ratio (SNR) of 63 dB for a signal with a bandwidth (BW) of 300 kHz, while dissipating only 130 μW from a 1.1 V power supply voltage, resulting in a figure-of-merit (FOM) of 213 fJ/conv.-step (simulated).