Design and tests of CMOS phase locked-loop

This paper presents the design and testing of already fabricated Phase-Locked Loop (PLL) in CMOS AMS 0.35μm technology with 3.3 V supply voltage. The PLL consists of Phase/Frequency Detector based on D flip-flops, charge pump, resonant Voltage-Controlled Oscillator, Frequency Divider and some additional blocks. The hold-in range of the PLL ranges from 2.35 to 2.65 MHz while the LC oscillator works with the frequency of 200 kHz. Simulations results were verified during tests and frequency characteristics of the VCO and PLL were plotted.