The design of low power low noise high speed CMOS readout front-end electronics for silicon strip detectors

This paper presents a design of low power and low noise, high speed analog readout front-end electronic system implemented in CMOS 180 nm UMC technology for silicon strip detector. The front-end readout channel architecture consists of charge sensitive amplifier (CSA), pole-zero cancellation (PZC) circuit and complex pulse shaping amplifier (shaper). The pulse shaping amplifier is a fifth order filter based on a follow-the-leader filter (FLF) architecture. The analog part of the system contains a 7-bit digital-to-analog converter (DAC), which reduces the DC offset spread from channel to channel of shaper output voltage. The designed readout front-end system characterizes low power dissipation P = 1.75mW per single channel. The peaking time (t_p) of the shaper is a programmable 60ns or 180ns. The complex shaper architecture allows us to obtain a shorter pulse width (the pulse width to peaking time is only t_0.01/t_p = 2.97) than in the case of standard CR-(RC)_n filter, and to operate with a higher rate of input pulses. Equivalent Noise Charge (ENC) of the front-end channel is equal to 880e^- for t_p = 60ns and 550e^- for t_p = 180ns obtained for the detector capacitance C_DET = 30pF.