Estimating performance penalty for various fault-tolerant techniques in multicore processors

The major trend to increase the computing performance in current processors is based on adding more and more cores on chip. Currently, processors with several cores are already available on the market and some researchers predict tenths or even hundreds cores on chip in the near future. On the other hand, the rising impact of process variations will lead to higher probability of faults which may become a major problem for manufacturers. One may suspect that soon manufacturers and designers will have to accept partially defective processors and use fault-tolerance techniques to guarantee a dependable chip operation. In this paper we investigate the impact of faults on multicore processor performance under the assumption that a faulty core or router on chip is detected and either repaired, replaced or disabled, according to appropriate fault-tolerant mechanism. We analyze various fault-tolerant techniques and simulate a 4×4 mesh multicore processor to quantify the performance penalty.