DocumentCode
3652030
Title
Performance of the bitonic mergesort network on a Dataflow computer
Author
Vukasin Ranković;Anton Kos;Sašo Tomažič;Veljko Milutinović
Author_Institution
Sch. of Electr. Eng., Univ. of Belgrade, Belgrade, Serbia
fYear
2013
Firstpage
849
Lastpage
852
Abstract
High speed computing and growing amounts of data are driving the quest for ever faster sorting algorithms. Sorting networks executing parallel sorting and dataflow computational paradigm are offered as a possible solution. In presented experiments Bitonic mergesort algorithm is implemented on an entry model of the Maxeler dataflow supercomputing system. Our results show, that sorting of a small size arrays on Maxeler, comparing to the fastest sorting algorithm on a CPU, achieves the speedup factor of 16. Using more advanced Maxeler systems, we expect to be able to sort larger arrays and achieve greater speedups.
Keywords
"Sorting","Algorithm design and analysis","Wires","Field programmable gate arrays","Educational institutions","Computers","Acceleration"
Publisher
ieee
Conference_Titel
Telecommunications Forum (TELFOR), 2013 21st
Type
conf
DOI
10.1109/TELFOR.2013.6716363
Filename
6716363
Link To Document