DocumentCode
3653056
Title
Fixed structure systolic array and processing of images
Author
M. Zajc;R. Sernec;J.F. Tasic
Author_Institution
Fac. of Electr. Eng., Ljubljana Univ., Slovenia
Volume
1
fYear
1998
Firstpage
96
Abstract
The paper presents a fixed structure systolic array for performing a set of computationally and real-time demanding problems that frequently arise in the area of image processing. The fixed structure systolic array implements Faddeeva´s (1959) algorithm, which could be interpreted as a generalised Gauss elimination. Modification of the algorithm is considered for improved stability and accuracy. The computations of the modified algorithm are presented in the form of a signal flow graph (SFG). This is followed with possible applications and additional extensions of the proposed systolic array structure.
Keywords
"Systolic arrays","Topology","Matrix decomposition","Hardware","Linear algebra","Image processing","Coprocessors","Computer interfaces","Computer networks","Least squares methods"
Publisher
ieee
Conference_Titel
Electrotechnical Conference, 1998. MELECON 98., 9th Mediterranean
Print_ISBN
0-7803-3879-0
Type
conf
DOI
10.1109/MELCON.1998.692347
Filename
692347
Link To Document