Scan Test of Die Logic in 3-D ICs Using TSV Probing

Prebond testing of through-silicon-vias (TSVs) and die logic is a significant challenge and a potential roadblock for 3-D integration. Built-in self-test solutions introduce considerable die area overhead. Oversized probe pads on TSVs to provide prebond test access limit both test bandwidth and TSV density. This paper presents a solution to these problems, allowing a probe card to contact TSVs without the need for probe pads, enabling both TSV and prebond scan test. Several possible prebond scan test configurations are shown-they provide varying degrees of test parallelism under design constraints. HSPICE simulations are performed on two logic-on-logic 3-D benchmarks. Results show that the ratio of the number of probe needles available for test access to the number of prebond scan chains determines which prebond scan configuration results in the shortest test time. Maximum prebond scan-in and scan-out shift-clock speeds are determined for dies in a benchmark 3-D design as a function of driver strength and transmission gate width. These clock speeds show that prebond scan test can be performed at a speed that is comparable with scan testing of packaged dies. The maximum clock speed can also be tuned by changing the drive strength of the probe and on-die drivers of the TSV network. Estimates are also provided for peak and average power consumption during prebond scan test for both a high-power pattern per scan chain and an average power pattern per scan chain. On-die area overhead for the proposed method is estimated to be between 1.0% and 2.9% per die for two 3-D benchmarks.