• DocumentCode
    3658789
  • Title

    Electromigration failure mechanism comparison between wafer level and package level reliability test on via structure

  • Author

    Wang Dulin;Ong Cheng Nee;Ng Hong Seng

  • Author_Institution
    X-FAB Sarawak Sdn. Bhd., 1 Silicon Drive Sama Jaya Free Industrial Zone, 93350 Kuching, Sarawak, Malaysia
  • fYear
    2015
  • Firstpage
    86
  • Lastpage
    89
  • Abstract
    Wafer level reliability (WLR) and package level reliability (PLR) test methods are widely used for Electromigration (EM) accelerated lifetime test. Both methods on different via structures are studied in this paper. The experimental result shows single via terminated EM structure lifetime is comparable between WLR and PLR methods based on Black´s equation; while stack via terminated structure lifetime is not homogeneous between the two methods. Physical failure analysis (PFA) also shows different failure mechanisms between WLR and PLR methods on stack via terminated structure. The hypothesis is that during WLR test, large joule heating is produced at stack via area due to W-via high resistivity. The temperature even is high enough to make the aluminum between stack vias melt or burnt out.
  • Keywords
    "Metals","Periodic structures","Failure analysis","Stress","Heating","Reliability","Electromigration"
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design (ASQED), 2015 6th Asia Symposium on
  • Type

    conf

  • DOI
    10.1109/ACQED.2015.7274013
  • Filename
    7274013