• DocumentCode
    3659178
  • Title

    Characteristics of inversion, accumulation and junctionless mode silicon N-type and P-type bulk FinFETs with optimized 3-nm nano-fin structure

  • Author

    Vasanthan Thirunavukkarasu;Yi-Ruei Jhan;Yan-Bo Liu;Yung-Chun Wu

  • Author_Institution
    Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan
  • fYear
    2015
  • fDate
    6/1/2015 12:00:00 AM
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    We for the first time evaluate the 3-nm gate Length (LG=3nm) inversion (IM) mode, accumulation (AC) mode and junctionless (JL) mode Silicon bulk FinFET performance with optimized nano-fin structure (FW=FH=3nm) using 3-D quantum transport device simulation. The excellent electrical characteristics of LG=3nm Si bulk FinFET are reported. The sub threshold slope values (SS~65mV/dec.) and drain-induced barrier lowering (DIBL<;17mV/V) are analyzed in all three IM, AC and JL modes bulk FinFET with |VTH| ~0.31 V. This research reveals that Moore´s law can be scaled down to 3-nm nodes.
  • Keywords
    "Silicon","FinFETs","Logic gates","Semiconductor process modeling","Mathematical model","Doping","Three-dimensional displays"
  • Publisher
    ieee
  • Conference_Titel
    Silicon Nanoelectronics Workshop (SNW), 2015
  • Type

    conf

  • Filename
    7275312
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3659178