A 100 Gb/s transimpedance amplifier with diode-connecting input-resistance-reduction in 32 nm CMOS technology

A 100 Gb/s transimpedance amplifier (TIA) for next generation optical communication adopts a diode-connected input-resistance-reduction architecture and is designed in 32 nm CMOS SOI technology. The proposed TIA design is based on a g_m-boosted common-gate amplifier with a diode-connected current source and incorporates a single-to-differential signal conversion architecture. The input resistance of the TIA is reduced while maintaining the gain. Post-layout simulation results show that the proposed TIA achieves the bandwidth of 72 GHz and the transimpedance gain of 38 dBΩ, which enables the data rate of 100 Gb/s. The TIA dissipates 27.6 mW under a supply voltage of 1.5 V.