Performance assessment of VeSFET-based SRAM

Power wall has become one of the main bottlenecks of future VLSI designs. A recently proposed junctionless twin-gate Vertical Slit Field Effect Transistor (VeSFET) is a low power and thermal friendly device, with highly regular layout, and two-side accessibility. These properties are critical for advanced 2D/3D technologies. SRAMs are fundamental blocks of VLSI systems, which are usually used for technology evaluation. This paper provides a VeSFET SRAM performance assessment modeled by CACTI, a cache modeling tool. The results show that VeSFET SRAM design is speed competitive to CMOS SRAM with about 40% of dynamic read energy consumption and 35% of total power consumption for read access rate 100MHz.