Run-time performance adaptation: Opportunities and challenges

Run-time performance adaptation with field delay testing is a promising approach for minimizing design margin while sustaining necessary operational margin in the field. However, run-time performance adaptation has not been adopted in industrial designs since a serious concern on timing error occurrence exists. First, this paper exemplifies the power reduction thanks to run-time performance adaptation with a 65nm test chip. Then, we introduce a stochastic framework to verify and optimize the run-time adaptation system in design time.