A low-power and area-efficient radix-3 SAR ADC

A new radix-3 Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is proposed in this paper. The proposed architecture reduces one Digital-to-Analog Converter (DAC) and one comparator in the implementation. The algorithm takes 2N comparison cycles to generate N ternary bits (trits). The proposed technique is applied to the design for 4 and 7-ternary bits using 65nm CMOS technology. The simulation results show that circuit consumes 0.9mW power and achieves a Signal-to-Noise Ratio (SNR) of 38dB for 4-trit case, 1.57mW power and 67dB SNR for 7-trit case. The Proposed circuit shows a power saving of 85% in control logic, less than 50% in overall circuit power dissipation and a more than 50% saving in total area for N-trit case when compared to conventional radix-3 architecture.