An error codes detection based background calibration for split SAR ADC

An error codes detection based background calibration technique is proposed to compensate for the non-linearity of Split SAR ADC. The nonlinearity suffered from the CDAC mismatch degrades SAR ADC performance in terms of DNL and INL. Calibration block detects both the missing and wide codes at ADC output, judges and then feeds back to adjust the compensation capacitor. A 9-bit SAR ADC with split CDAC has been implemented in standard 65 nm CMOS technology. Simulation results show that it achieves a peak SNDR of 54.7 dB and 0.843 mW from a 1.2 V power supply. +0.20/-0.11 LSB DNL and +0.15/-0.15 LSB INL are improved after calibration.