Statistical variability and sensitivity analysis of dual-k spacer FinFET device-circuit co-design

High-ft spacer materials have been extensively researched for the suppression of short-channel effects (SCEs) in nano-scaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance. The dynamic performance with enhanced device electrostatics can be effectively improved by dual-k spacer (SymD-fc) architecture. However, this architecture in sub-20nm node requires special attention towards their performance under process induced variations. For the first time, this paper explores the tolerance of SymD-k architecture and its circuit/SRAM performance under random statistical variations and sensitivity analysis of device parameters. It is observed from the obtained 2D results that the SymD-k device/circuit exhibits least sensitivity to random variations in comparison to the conventional FinFETs.