Influences of k values of gate dielectric and buried insulator on subthreshold slope of UTB SOI MOSFETs

A model on subthreshold slope of UTB SOI MOSFETs is established and its validity is confirmed by comparing with the simulated results from technology computer aided design. Using the model, the impacts of k values of the gate dielectric and buried insulator on the subthreshold slope of the device are discussed. The results show that the subthreshold behaviors will be degraded when high-k gate dielectric is used due to enhanced fringing field effect, and however, can be improved by using low-k buried insulator.