Ultra-low power delta sampling SAR ADC for sensing applications

This paper presents a novel successive approximation register analog-to-digital converter (SAR ADC) with delta sampling for low power sensing applications. By reducing the binary search range, the proposed SAR ADC is able to consume much lower power than the conventional SAR ADC. The proposed SAR ADC is designed using the 0.18-μm CMOS technology. When applied to neural signal acquisition, with a 1-V supply voltage, the proposed ADC consumes merely 212-nW of power while achieving 7.4 effective number of bits (ENOB). When compared against the conventional SAR ADC, the proposed SAR ADC achieved an impressive 83% in power saving.