• DocumentCode
    3664698
  • Title

    Process variation immune dopingless dynamically reconfigurable FET

  • Author

    Saurabh Bhaskar;Jawar Singh

  • Author_Institution
    Department of Electronics and Communication Engg., PDPM IIITDM, Jabalpur, India
  • fYear
    2015
  • fDate
    6/1/2015 12:00:00 AM
  • Firstpage
    257
  • Lastpage
    260
  • Abstract
    In this paper, a novel concept of dynamic reconfiguration of field-effect transistor (FET) having capability to switch between tunnel FET (TFET) and metal-oxide-semiconductor FET (MOSFET) is proposed. The proposed device yields the advantages of both devices (low power TFET and high performance MOSFET). To embrace best features into a single device, charge-plasma (CP) and electro-static polarity techniques were employed. The proposed device comprises of ultrathin intrinsic (dopingless) silicon nanowire, where source and drain regions are formed by CP and polarity-gate (PG). The dopingless and junctionless concepts provide advantage of process variation immunity mainly arises from random dopant fluctuation (RDFs) and lower thermal budget (thermal annealing and ion implantation process) that minimizes the fabrication cost.
  • Keywords
    "MOSFET circuits","Logic gates","MOSFET","Tunneling","Silicon","Electrodes"
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices and Solid-State Circuits (EDSSC), 2015 IEEE International Conference on
  • Print_ISBN
    978-1-4799-8362-9
  • Type

    conf

  • DOI
    10.1109/EDSSC.2015.7285099
  • Filename
    7285099