Abnormal off-state current in multiple silicon nanowire MOS transistors

This work reports the observation of abnormally large off-state currents in silicon nanowire transistors with gate length less than 2.5 μm. As the gate lengths as well as the source/drain doping level were well beyond the punchthrough conditions, we ascribed this observation to the charge transport along the corners/boundaries of the nanowires. Temperature dependent characteristics were also investigated. The threshold voltage decreases linearly as the temperature increases which is ascribed to the charge states at oxide/nanowire interfaces. Corner and surface of nanowire thus play an important role for ultra-short nanowire transistors and that calls for shape of nanowire optimation for device design.