A 56-to-66 GHz quadrature phase-locked loop with a wide locking range divider chain in 65nm CMOS

A low power and low phase noise phase-locked loop (PLL) is proposed in this paper to provide a quadrature millimeter-wave source for the 60GHz direct-conversion transceiver. An in-phase injection-coupled quadrature voltage controlled oscillator (IPIC-QVCO) [1] whose symmetric coupling structure is composed of four diode-connected transistors is implemented to optimize both phase noise and phase error. Besides, a novel feedback is proposed in the QVCO to reduce phase noise while remaining the oscillation frequency range unchanged. This PLL employs divider chain with a wide locking range consisting of a digitally controlled injection-locked frequency divider (ILFD) with a 2-bit binary-weighted switch-capacitor bank, 3 current mode logic (CML) dividers, and a multiple modulator divider (MMD). The proposed PLL is designed with a 65nm CMOS technology, and the QCVO achieves a tuning range of 16.39% from 55.95GHz to 65.94GHz with a phase noise of -97.5dBc/Hz at 1MHz offset while consuming 12mW of power. Extensive simulation show that the PLL achieves an excellent phase noise performance of -92dBc/Hz at 1MHz offset and covers all the four required frequency in IEEE802.11ad (58.32GHz, 60.48GHz, 62.64GHz, and 64.80GHz, respectively.) while consuming only 30mW of power from a 1.2 V supply.