FieldRC, a GPU accelerated interconnect RC parasitic extractor for full-chip designs

This paper describes FieldRC, a fast and accurate, Design-for-Manufacturing (DFM) aware, Monte-Carlo (MC) based parasitic extractor for computing interconnect capacitance (C) and resistance (R) in VLSI designs. A novel rejection sampling technique rapidly solves capacitance in multiple dielectric environments using a small memory footprint (~2GB) even for large designs to 200K nets. For the first time a MC solver is used to calculate wire R, allowing accurate and efficient chip level evaluation of node level network resistance. The FieldRC extraction core has also been mapped to Graphical Processor Units (GPU) to further accelerate the speed of RC calculation. Although implementation of a MC based capacitance extraction algorithm using off-the-shelf GPU video graphic cards in a standard PC has been reported [1-2] this work extends the GPU´s speed to both R and C implementation. With this hardware acceleration, an accurate wire RC can be calculated at a speed comparable to coarse model-based industry extractors. Even a single 2 GPU ($1000) workstation with an Intel 2 GHz Xeon processor can extract the field-solved RC parasitic of IM net designs in a few hours.