Noise optimization of switched capacitor integrator

The paper presents a method of noise optimization for a type of classical switched-capacitor(SC) integrators to design the distribution plan of capacitors in a specific layout area. The OP utilized in the SC integrator is a two-stage OP. Thus there are three significant capacitors, two of which are sampling capacitors and one of which is the compensation capacitor in the OP. Using small signal model, noise model of positive integrator and negative integrator are established, respectively, which are expressed in transfer functions to find the optimal distribution of capacitors. The noise analysis is validated by a time-domain simulation, corresponding well with each other. The result shows that the positive integrator has same noise performance as the negative integrator and under the limit of 30um × 30um layout area with TSMC 0.18um mixed-signal process and under the 10 AR and 0.1% DE demand the two sampling capacitors and the compensation capacitor should be 1pF, 0.lpF and 0.7pF, respectively to achieve an optimal noise performance with satisfying the speed demand simultaneously with 10 stages of integration and sampling capacitor ratio.