Ultra high-performance ASIC implementation of SM2 with power-analysis resistance

In this paper, we propose a high-performance implementation of elliptic curve cryptography over SCA-256 prime field by introducing an all-new isochronous architecture, which can also resist power-analysis attack. By modifying Montgomery ladder-based scalar multiplication, point addition (PA) and point double (PD) can operate synchronously, resisting simple power analysis (SPA) and double attack with minimum time-cost. Then PA and PD are designed to be strictly isochronous units by matching our configurable modular multiplication unit of pipelined stage. Both algorithm and hardware schedule are optimized from bottom to up, random cycles are also inserted to resist differential power analysis (DPA). In the hardware evaluation using CMOS standard cell library of 0.13μm, our ECC processor achieves 211μs and 8.5μJ for one scalar multiplication with 208k gate counts. Compared to other related designs, our architecture offers not only 2~6 times better area-time product but also great power-analysis resistance.