Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS

This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Floating body technique and stacked nMOSFETs are utilized to improve the power handling capability and isolation performance. The fabricated SPDT switch IC has exhibited an input referred 0.5-dB compression point of 21.8 dBm, an isolation of 42.4 dB and an insertion loss of 1.2 dB for transmit mode at an operation frequency of 5.0 GHz. The SPDT switch IC has an insertion loss of 2.1 dB and a return loss of 10.6 dB for receive mode at 5.0 GHz.