Reliability aware simulation flow: From TCAD calibration to circuit level analysis

In this paper, we present a simulation flow based on TCAD model calibration against experimental transistor measurement and doping profile reverse engineering. Further the physical astatistical variability simulations at TCAD level are also adjusted to match the statistical measurement. This is folloed up by oxide wear out reliability characterization and modelling. Finally statistical compact model libraries for fresh and aged devices are extracted from large samples of TCAD simulation results allowing the performance analysis of a 6T SRAM cell. The calibration procedure has been performed on P and NMOS transistors fabricated and characterized by IMEC, while Glasgow University performed the TCAD reverse engineering and calibration, and the statistical simulations using dedicated Gold Standard Simulations tools.