Interplay between quantum mechanical effects and a discrete trap position in ultra-scaled FinFETs

In this work we establish a link between positions of a single discrete charge trapped in an oxide interface and between the performance of ultra-scaled FinFET transistors. The charge trapped in the oxide induces gate voltage shift (ΔV_G). This ΔV_G is presented as a function of the device geometry for two regimes of conduction - from a sub-threshold to an ON-state. For specific trap positions in the oxide, we show that the trap impact decreases with scaling down of the FinFET size and of the applied gate voltage. We also compare the Drift-Diffusion (DD) calculations with the Non Equilibrium Green Functions (NEGF) simulations in order to investigate the importance of quantum charge confinement in transport and of reliability resilience in ultra-scaled non-planar transistors, such as FinFETs.