A generic approach for capturing process variations in lookup-table-based FET models

We propose a generic approach for introducing process variations (e.g., die-to-die, wafer-to-wafer, lot-to-lot) into lookup-table-based, FET compact models. The output of the models has been carefully verified with TCAD simulation results for both conventional MOSFETs and Tunnel FETs. It is clear that this approach enables circuit-level analysis of novel transistors with the consideration of various process variation sources.