• DocumentCode
    3667953
  • Title

    A physics-based compact model for Fully-Depleted Tunnel Field Effect Transistor

  • Author

    S. Martinie;O. Rozeau;C. Le Royer;J. Lacord;M-A. Jaud;T. Poiroux;G. Le Carval;J-C. Barbe

  • Author_Institution
    CEA-LETI, 17 rue des Martyrs, 38054 Grenoble, Cedex 9, France
  • fYear
    2015
  • Firstpage
    313
  • Lastpage
    316
  • Abstract
    Tunnel FETs (TFET) are promising candidates for integration in logic circuits at very low supply voltages. We report here a SPICE compact model that describes all regimes of the TFET transistor. The current contribution from source and drain sides is described by an original set of equations including the electrostatic behavior and the effect of superlinear onset. Finally, this model is implemented using Verilog-A language and compared with TCAD simulations.
  • Keywords
    "Mathematical model","Tunneling","Electrostatics","Electric potential","Transistors","Capacitance","Logic gates"
  • Publisher
    ieee
  • Conference_Titel
    Simulation of Semiconductor Processes and Devices (SISPAD), 2015 International Conference on
  • ISSN
    1946-1569
  • Print_ISBN
    978-1-4673-7858-1
  • Type

    conf

  • DOI
    10.1109/SISPAD.2015.7292322
  • Filename
    7292322
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3667953