Channel-potential based compact model of Double-Gate Tunneling FETs considering channel-length scaling

A channel-potential based compact I-V model for Double-Gate Tunneling FETs (DG-TFETs) incorporating channel length scaling is presented. The model covers both sub-threshold and strong-inversion operation regimes and achieves good agreement with TCAD results while the channel length is scaled down to 10nm. The effect and mechanism of channel length scaling on the performance of DG-TFETs are investigated. As expected, the scaling down of channel length deteriorates off-state and sub-threshold performance of DG-TFETs and leads to worse output saturation characteristics. However, our compact model provides a quick and quantitative means to assess the impact of TFET scaling on the device performance.