DocumentCode
3667978
Title
Lithography process model building using locally linear embedding
Author
Pardeep Kumar;Alan E. Rosenbluth;Babji Srinivasan;Ramya Viswanathan;Nihar R. Mohapatra
Author_Institution
Indian Institute of Technology-Gandhinagar, VGEC Campus, Chandkheda, Ahmedabad, Gujarat, India
fYear
2015
Firstpage
413
Lastpage
416
Abstract
Practical models of lithographic processes are usually empirically calibrated, making their accuracy dependent on the total number of samples used to build the models, and more specifically on the selection of a representative set of samples for calibration. An inadequate number of samples can adversely impact model accuracy, but a broadly comprehensive set will excessively increase measurement cost. Lithography process models based on samples which are picked uniformly from populated regions of the original pattern space and are truly a representative set will improve model prediction accuracy, as is highly desirable for model based optical proximity correction (OPC) simulations. We propose a robust approach for sample plan selection for lithography process model building using locally linear embedding (LLE). The effectiveness of the proposed method is verified by simulating some critical layers in 14-nm and 22-nm complementary metal oxide semiconductor (CMOS) technology nodes. Experimental results show that without compromising model accuracy, LLE can provide a competitive representative sample plan selection in a single shot, in comparison with hundreds of random cross-validation experiments as an alternative.
Keywords
"Data models","Computational modeling","Semiconductor device modeling","Accuracy","Calibration","Buildings","Lithography"
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices (SISPAD), 2015 International Conference on
ISSN
1946-1569
Print_ISBN
978-1-4673-7858-1
Type
conf
DOI
10.1109/SISPAD.2015.7292348
Filename
7292348
Link To Document