Power-performance-area engineering of 5nm nanowire library cells

We benchmark planar MOSFETs, FinFETs, and nanowires in a wide range of design rules, spanning from 90nm down to 2nm. This benchmarking evaluates inverter switching speed for a load of 70 metal pitches long interconnect wire and a fan-out of one. Planar MOSFET logic slows down sharply at 14nm design rules, mainly due to short-channel effects reducing the driving strength at a fixed off-state leakage level. FinFETs take over at 14nm node and continue providing incremental gains down to 7nm design rules, but slowing down at 5nm due to the dominant parasitic middle-of-line capacitance. Vertical nanowires take over the lead at 5nm design rules and scale gracefully down to at least 5nm node. Based on these results, we perform detailed benchmarking of several design and process options for a 2-input NAND logic cell built on vertical nanowires with 5nm design rules. Benchmarking involves a holistic modeling methodology with 3D advanced carrier transport characterization of the nanowire behavior, 3D extraction of parasitic RC in the library cell, and simulation of power and delay of an 11-stage ring oscillator in HSPICE. Different cell designs and material engineering options offer cell area reduction of 33% with delay and power changing by over 2x.