Some aspects on modeling of the signal and power integrity in a PCB based on waveform analysis

This paper presents some of the issues of signal and power integrity in relation with appropriate modeling and simulation methods that are available. The clock signal of a communication protocol is experimentally tested in order to find the rules to improve its signal integrity (SI) along the paths on the printed circuit board (PCB). The signal and power integrity of this PCB are improved using a set of experimental rules based on results of an experimental case study over signal routes. The experimental results obtained are compared with those given by the auto routing function of the design environment. Thus, some improvements of signal integrity along the route clock are highlighted. This set of rules applied to PCB design is validated by the experiment and simulation results.