• DocumentCode
    3674573
  • Title

    Modeling of parallel electric field tunnel FETs

  • Author

    K. Fukuda;Y. Morita;T. Mori;W. Mizubayashi;M. Masahara;T. Yasuda;S. Migita;H. Ota

  • Author_Institution
    National Institute of Advanced Industrial Science and Technology, AIST Tsukuba, Ibaraki, Japan
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Tunnel FETs with vertical tunnel paths are fabricated and successfully modeled by the nonlocal band to band tunneling model. Although enhancement of ON currents are obtained by longer source gate overlap lengths, the increase of the ON current is less than proportional to the overlap lengths, because of non-uniformity of the band to band tunneling generation rates. The behavior of this type of tunnel FETs is precisely explained by the device simulation model. The key point is the peak generation rates at the source edge.
  • Keywords
    "Logic gates","Semiconductor process modeling","Electric fields","Yttrium","Field effect transistors","Silicon","Semiconductor device modeling"
  • Publisher
    ieee
  • Conference_Titel
    Computational Electronics (IWCE), 2015 International Workshop on
  • Type

    conf

  • DOI
    10.1109/IWCE.2015.7301959
  • Filename
    7301959
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3674573