An embedded approach to visual prosthesis chip

Age related macular degeneration and retinitis pigmentosa are two most common cause for loss of sight. In this paper an architecture of a processor has been described for 64 electrode implantable retinal prosthesis chip. The processor takes serial data and generates PWM signals according to the serially received data. This paper describes basically the design and implementation of a UART (Universal Asynchronous Receiver and Transmitter) module, dual port RAM module, a controller module and PWM signal generator module. The processor has been designed with Verilog HDL and synthesized on Altera DE0 nano board. Singaltap logic analyser has been used for the debugging purpose.