• DocumentCode
    3679831
  • Title

    Reduced common mode voltage based DC-bus voltage balancing algorithm for three-level neutral point clamped (NPC) inverter drive

  • Author

    Abhijit Choudhury;Pragasen Pillay

  • Author_Institution
    Power Electronics and Energy Research (PEER) Group, P. D. Ziogas Power Electronics Laboratory, Department of Electrical and Computer Engineering Concordia University Montreal, Quebec H3G 1M8, Canada
  • fYear
    2015
  • Firstpage
    4496
  • Lastpage
    4501
  • Abstract
    A reduced common mode voltage (CMV) based DC-link voltage balancing strategy is proposed for a neutral point clamped (NPC) three-level inverter with permanent magnet synchronous machine. Compared to the earlier proposed strategy, it completely eliminates the Vdc/2 corresponding CMV by eliminating the two zero voltage vectors (PPP, NNN) from the space vector switching sequences. Hence, it uses only one zero voltage (OOO) vector with the other redundant voltage vectors to produce the reference vector in inner subsectors. Detailed simulation and experimental studies are also carried out to show the effectiveness of the proposed system with DC-link voltage balancing ability. Harmonic distortions are also compared with the previously proposed scheme. Dspace® based real time operating system is used for real time implementation with 6.0 kW surface PMSM.
  • Keywords
    "Inverters","Capacitors","Torque","Switches","Voltage control","Harmonic distortion","Modulation"
  • Publisher
    ieee
  • Conference_Titel
    Energy Conversion Congress and Exposition (ECCE), 2015 IEEE
  • ISSN
    2329-3721
  • Electronic_ISBN
    2329-3748
  • Type

    conf

  • DOI
    10.1109/ECCE.2015.7310294
  • Filename
    7310294