DocumentCode
3683151
Title
Practical methodology for the extraction of SEED models
Author
Collin Reiman;Nicholas Thomson;Yang Xiu;Robert Mertens;Elyse Rosenbaum
Author_Institution
Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 1308 W. Main St., 61801 USA
fYear
2015
Firstpage
1
Lastpage
10
Abstract
A custom test board facilitates TLP characterization of the external pins of an integrated circuit. Models extracted from the data are used to simulate the pin-level response of the IC to an IEC 61000-4-2 discharge. ESD gun zaps are applied to the test board; simulated and measured waveforms are compared.
Keywords
"Pins","Current measurement","Voltage measurement","Semiconductor device measurement","Transmission line measurements","Electrostatic discharges","Pulse measurements"
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2015 37th
Type
conf
DOI
10.1109/EOSESD.2015.7314789
Filename
7314789
Link To Document